In order to continue to improve performance and functionality of integrated circuits, the industry has recently been developing technology to enable vertical integration of semiconductor device chips, known generally as three-dimensional (3D) stacking technology. The stacked substrates may be full or partial wafers, each typically having multiple chips. A 3D stack can be diced after bonding to separate the units, each unit having two or more chips vertically bonded together. Typically, a semiconductor chip includes several layers of integrated circuitry (e.g., processors, programmable devices, memory devices, etc.) built on a semiconductor substrate. A top layer of the bonded stack may be connected to a bottom layer of the stack utilizing through substrate interconnects or vias (TSVs). Formation of the TSV is recognized as a particular challenge (see e.g., Dukovic, et. al., Through-Silicon-Via Technology for 3D Integration).
Among other issues, a via extending through a semiconductor substrate must generally have a high aspect ratio. Forming such a deep feature without damaging the remaining substrate, and then forming a conductive path within the deep feature that is electrically insulated from the substrate is extremely difficult. Some have proposed to etch the hole in the substrate, and then expose the substrate to very high temperatures whereby an oxide layer is formed over the entire exposed surfaces that is a reliable insulating layer. Such temperatures are incompatible with CMOS BEOL (back-end-of-the-line) processing, so such forming an oxide layer must be done in a “via first” scheme before any semiconductor devices (FEOL) or interconnect wiring (BEOL) are formed (see Andry et al, US 2010/0032764). Copper is preferred for TSVs due to its high conductivity. However, ‘via first’ schemes are problematic with copper vias because semiconductor devices are highly susceptible to damage as a result of copper migration into the substrate.
Copper is more compatible with back end or ‘via middle’ processing, but the thermal expansion mismatch between the copper of a TSV and the surrounding materials can create excessive thermal stress and cause cracking Edelstein et al., U.S. Pat. No. 7,276,787 (“the '787”), suggests to address this problem by utilizing an annular TSV. Specifically, the '787 teaches to etch a large hole, form a series of layers on the sidewalls without filling the hole (e.g., electrical insulator, various barrier layers, a conductive layer, and further isolation layers). Finally, the core of the hole can be filled by a material selected to have thermal characteristics similar to the substrate such that overall structure has an effective CTE which closely matches the CTE and elastic modulus of the substrate.
However, even an annular copper TSV tends to extrude when subjected to thermal cycling during CMOS BEOL processing (see, e.g., Cho, “Technical Challenges in TSV Integration”). Extrusion by a TSV can stress overlying metallization layers, weakening or shorting any embedded interconnect wiring. Cho provides SEM photographs showing extrusion of a copper TSV resulting from exposure to process temperatures for formation of interconnect metallization (BEOL). The damage caused by such extrusion is depicted in FIGS. 1A and 1B. FIG. 1A shows that the copper core of a solid TSV 110 has extruded above the CMP'd surface 104 of passivation layer 102, lifting overlying layers 120 and stressing the interconnect wiring 122 embedded therein. FIG. 1B illustrates crack 105 through the inner core and crack 106 initiating at the lower inner corners of annular copper TSV 130. Cho recommends to minimize copper extrusion by forming the via last.
While ‘via last’ processing generally proceeds at temperatures low enough to avoid copper extrusion, ‘via last’ consumes the entire TSV footprint though all BEOL layers, making it is far less efficient for purposes of process integration and chip design. It would be highly advantageous to identify a technique to form a reliable copper TSV that could be formed during BEOL processing.